Compact AI Accelerator IP for Embedded AI and Intelligent Computing
Built for Compact AI Acceleration
APARAJIT Micro is the entry-level configuration in the APARAJIT AI Accelerator IP family. It combines one AJIT Processor Core with one APARA AI Accelerator Core, providing a compact semiconductor platform for AI inference, tensor processing, and embedded computing applications.
APARAJIT Micro is designed for organisations developing embedded AI platforms, robotics, IoT inferencing, and signal processing applications requiring programmable processing together with dedicated AI acceleration.

1 + 1
5-Const.
GNSS SUPPORT
256 Ops/Cyc
PEAK (FP4 / INT4)
4 × MIMD
INDEPENDENT THREADS
256-bit
LOAD / STORE WIDTH
Compact acceleration, common architecture.
Compact AI-enabled semiconductor platforms require programmable processing together with dedicated AI acceleration within an efficient System-on-Chip (SoC) architecture.
APARAJIT Micro combines one AJIT Processor Core with one APARA AI Accelerator Core to provide programmable processing and AI acceleration within a common semiconductor architecture.
As part of the APARAJIT product family, APARAJIT Micro maintains software portability across Micro, Mini, and Mega configurations, enabling engineering teams to scale product development while maintaining a consistent development workflow.
APARAJIT Micro is designed for organisations developing embedded AI platforms, robotics, IoT inferencing, and signal processing applications requiring programmable processing together with dedicated AI acceleration.
| Specification | APARAJIT Micro |
| AJIT Processor Cores | 1 |
| APARA AI Accelerator Cores | 1 |
| GNSS Support | 5-Constellation GNSS |
APARA AI Accelerator performance and architecture.
Compute Performance
| FP4 / INT4 | 256 Ops/Cycle |
| FP8 / INT8 | 128 Ops/Cycle |
| FP16 / INT16 | 64 Ops/Cycle |
| FP32 / INT32 | 16 Ops/Cycle |
| FP64 / INT64 | 8 Ops/Cycle |
APARA Architecture
| Execution Model | 4 Independent MIMD Threads |
| Hardware Execution Lanes | 8 |
| Instruction Cache | 16 KB Bundled Instruction Cache |
| Memory Banks | 4 Parallel Memory Banks |
| DMA | Dedicated DMA Engine |
| Load / Store Width | 256-bit |

One unified semiconductor architecture.
The APARA AI Accelerator architecture incorporates four independent MIMD threads, eight hardware execution lanes, four parallel memory banks, a dedicated DMA engine, a bundled 16 KB instruction cache, and a 256-bit load/store interface. It supports AI inference, tensor processing, and parallel computing across FP4/INT4, FP8/INT8, FP16/INT16, FP32/INT32, and FP64/INT64 precision formats.
As a member of the APARAJIT AI Accelerator IP family, APARAJIT Micro shares a common hardware and software architecture with APARAJIT Mini and APARAJIT Mega, enabling software portability and scalable product development across deployment configurations.
What APARAJIT Micro provides.
One AJIT Processor Core
One APARA AI Accelerator Core
Includes one APARA AI Accelerator Core designed for AI inference, tensor processing, and parallel computing workloads
Common APARAJIT Architecture
Shares the same hardware and software architecture as APARAJIT Mini and APARAJIT Mega, enabling software portability across the product family.
Integrated Memory Architecture
Four parallel memory banks, a dedicated DMA engine, a bundled 16 KB instruction cache, and a 256-bit load/store interface for efficient data movement.
Multiple Precision Support
Supports FP4/INT4, FP8/INT8, FP16/INT16, FP32/INT32, and FP64/INT64 precision formats for AI inference, tensor processing, and parallel computing.
– Applications
Where APARAJIT Micro fits.
Drones
Robotics
IoT Inferencing
Signal Processing
Accelerates signal processing workloads across embedded and intelligent semiconductor platforms.
– Why choose APARAJIT Micro
Why Choose APARAJIT Micro?
- One AJIT Processor Core
- 5-Constellation GNSS Support
- Software Portability Across the APARAJIT Product Family
- Licensable Semiconductor IP for Custom System-on-Chip (SoC) Integration
- One APARA AI Accelerator Core
- Common APARAJIT Architecture
- Multiple Floating-Point and Integer Precision Formats
– Inside the stack
Explore the Complete Architecture
APARAJIT AI Accelerator IP provides dedicated AI acceleration for intelligent semiconductor platforms, while AJIT Processor Core IP delivers programmable processing, system control, and System-on-Chip (SoC) management.
Together, they form the Powai Labs semiconductor IP portfolio, enabling intelligent computing across embedded systems, robotics, industrial automation, defence, aerospace, navigation technologies, and AI-enabled semiconductor platforms.
