AJIT PROCESSOR
AJIT Processor Core IP for Embedded Systems and SoC Design
Indigenous Processor Core IP for Programmable Computing
AJIT Processor Core IP is a configurable RISC-based processor core developed for programmable processing, system control, memory management and System-on-Chip (SoC) development.
The processor architecture supports integration with memory subsystems, peripheral IP, debug infrastructure and accelerator technologies, providing a programmable processing foundation for embedded and intelligent semiconductor systems.
AJIT PROCESSOR ARCHITECTURE
Built on the SPARC-V8 Instruction Set Architecture
The AJIT processor implements the SPARC-V8 instruction set architecture. The AJIT processor family includes two documented CPU variants:
AJIT CPU32
Based on the SPARC-V8 ISA.
AJIT CPU64
Based on SPARC-V8 with 64-bit and vector extensions.
The architecture supports single-core and multi-core processor configurations, with single-thread and multi-thread implementations documented in the AJIT Processor Family manual.
KEY PROCESSOR FEATURES
Designed for Configurable SoC Integration
The documented AJIT architecture includes:
MEMORY & SYSTEM INTERFACES
Built for Integration Across the SoC
AJIT incorporates a Memory Management Unit and configurable instruction and data cache architecture.
The processor core provides a 64-bit AJIT-CORE-BUS (ACB) interface, with bridges available for AXI and AHB interfaces. It also provides interrupt, debug, reset and processor-mode interfaces.
Peripheral Integration
The documented peripheral IP ecosystem includes:
- UART
- SPI
- IĀ²C
- SPI PSRAM Controller
- Bus Network-on-Chip (NoC)
- Interface Bridges
EXCEPTION & INTERRUPT HANDLING
Precise Exception Management
An AJIT CPU supports the exceptions defined by the SPARC-V8 standard, including hardware and software-generated exceptions.
Each CPU can respond to 15 interrupt levels, with vectored trap handling and precise exception handling. The documented minimum trap and interrupt latency is 12 clock cycles.
DEBUG & DEVELOPMENT SUPPORT
Tools for Software Development and System Validation
AJIT includes dedicated debugging capabilities through:
- Debug Support Unit
- AJIT Debug Monitor
- GDB remote debugging
- Serial UART or JTAG debug interface
- Interrupt Controller
- Optional Performance Monitor
The development environment includes a processor emulator written in C and FPGA prototypes of the documented processor configurations.
SOFTWARE ECOSYSTEM
A Development Environment Around AJIT
The AJIT software development chain includes:
Development Tools
- GCC / G++
- GNU Binutils
- GDB
Operating Systems / RTOS
- CORTOS-2
- FreeRTOS
- RTEMS
- Zephyr
- Linux
The AJIT Manual specifically documents compatibility with GCC, GDB and the Linux kernel for the SPARC-V8 ISA, along with CORTOS-2 and supporting development tools.
ASIC & SILICON HISTORY
From Processor Development to Fabricated Silicon
AJIT’s documented development includes ASIC implementation work.
180 nm Proof of Concept
A proof-of-concept implementation of the AJIT processor core was carried out at SCL Chandigarh in 180 nm technology.
Documented details:
7 mm Ć 7 mm
144 functional I/Os
256-pin package
0.5 W at 66 MHz at the slow corner
65 nm NAVIC GPS + IRNSS Receiver SoC
An implementation of the AJIT processor core for a NAVIC GPS + IRNSS receiver SoC was fabricated in 65 nm technology at UMC, Taiwan.
The AJIT Manual states that the SoC was completely functional based on first-silicon testing.
The documented SoC measured 4 mm Ć 4 mm, with the CPU occupying approximately 1 mm Ć 1 mm.
APPLICATIONS
Processor Technology for Embedded and Intelligent Systems
The current Powai Labs product material identifies AJIT applications across:
- Embedded Systems
- Robotics
- Industrial Automation
- Defence Electronics
- IoT Devices
- Navigation Systems
AJIT can also be integrated alongside accelerator technologies, including the APARAJIT AI Accelerator, within custom SoC architectures.
AJIT + APARAJIT
Programmable Processing Meets AI Acceleration
AJIT provides the programmable processing foundation, while APARAJIT adds dedicated AI acceleration for AI inference, tensor processing and parallel computing.
The two technologies can therefore form complementary components within an intelligent SoC architecture.
WHY AJIT
A Processor Architecture With a Documented Development History
- SPARC-V8 based architecture
AJIT CPU32 and CPU64 implementations. - Configurable processor family
Single-core, multi-core, single-thread and multi-thread configurations. - Integrated system capabilities
Memory management, cache, interrupts, debugging and peripheral interfaces. - Development ecosystem
GCC, GDB, Linux, CORTOS-2 and additional software-development tools. - ASIC implementation history
Documented 180 nm and 65 nm implementations.
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