High-Speed SerDes Design Engineer

High-Speed SerDes Design Engineer

Team Lead / Manager

  • 5-15 Years
  • Bachelor / Masters (Electrical/Electronics)
  • Engineering
  • Mumbai, Maharashtra (Hybrid)

A strong SerDes architecture engineer will demonstrate deep expertise in high‑speed analog/mixed‑signal design, DSP‑based equalization, protocol‑level understanding, and silicon‑proven experience across 28G–224G SerDes generations.

Required Skills and Knowledge

High‑speed analog front‑end design: CTLE, DFE, samplers, comparators, CDR loops.
Transmitter architecture: pre‑emphasis, de‑emphasis, swing calibration, PAM4 drivers.
Clocking systems: PLLs, phase interpolators, duty‑cycle correction, jitter optimization.
DSP & equalization algorithms: adaptation, FEC interfacing, link‑training logic.
Protocol compliance: PCIe Gen4/5, USB 3.x/4, Ethernet (OIF‑CEI), HDMI/DP, UCIe.
System‑level SI/PI co‑design: IBIS‑AMI modeling, channel loss analysis, jitter decomposition.
Silicon bring‑up & characterization: eye diagrams, BER testing, jitter breakdown.
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