| IMAGE Features:
| Design Language |
VHDL/Verilog
|
|
Testbench Language
|
VHDL/Verilog/System C/C
|
| Software Simulator
|
NC-Sim®, Modelsim®, VCS® |
| ASIC Gate Capacity
|
1 to 40 Million ASIC Gates
|
| Memory Capacity
|
Each Card supports 24 MB SRAM
|
| Memory Extraction |
Automatically maps embedded design memory onto external memory bank for better FPGA utilization. |
| Performance
|
1000X
|
| Co-modeling option
|
API, PLI
|
Debug
a) Internal Signal Observeabilit
b) Internal Signal Controllability
|
|
| Monitors any signal in the entire design
|
Forces any signal to any desired value
(e.g. stuck-at-zero or stuck-at-one
)
|
| Path to Emulation
|
Yes
|
|
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